Technology
Performance
CHERI performance is a property of a complete implementation and workload: microarchitecture, capability width and compression, caches, memory, ABI, compiler, operating system and compartment design all contribute.
Why it matters
Useful performance evidence shows where time and space change and whether security benefits justify the trade-off for the target product.
In brief
CHERI performance is a property of a complete implementation and workload: microarchitecture, capability width and compression, caches, memory, ABI, compiler, operating system and compartment design all contribute. There is no single universal overhead number.
Key considerations
1. Baseline
Compare equivalent, optimised workloads on documented hardware and software configurations.
2. Measure
Include latency, throughput, memory footprint, code size, cache behaviour and compartment-transition costs where relevant.
3. Explain
Separate architectural effects from prototype limitations, compiler maturity, porting choices and benchmark artefacts.
Evidence and caveats
Results from Morello, FPGA or one ABI should not be generalised to future silicon or a different CHERI architecture without evidence.
Use the exact architecture and software specification implemented by the target. Separate architectural guarantees from system-level outcomes.