RISC-V and embedded development

Why it matters

This thread matters because embedded products have long lifetimes, native code and strong isolation needs but different memory, power and real-time constraints.

In brief

RISC-V provided an open architecture context for CHERI research and implementation, while CHERIoT adapted capability principles for constrained embedded systems. FPGA platforms, processor IP, SDKs and silicon have broadened routes beyond application-class demonstrators.

RISC-V made it possible to explore CHERI across open processor implementations and different workload classes. Embedded routes such as CHERIoT should be evaluated on their own constraints—real-time behaviour, memory, peripherals and compartment model—rather than as smaller versions of an application-class system.

Key considerations

1. Architecture work

CHERI-RISC-V specifications and implementations explored capabilities in 32- and 64-bit RISC-V.

2. Embedded profile

CHERIoT combined a compact capability model with fine-grained compartments and an RTOS-oriented software stack.

3. Ecosystem

Open platforms and commercial suppliers created practical routes for evaluation and product development.

Evidence and caveats

RISC-V CHERI and CHERIoT are related but not interchangeable targets. Check the exact ISA, ABI and software model.

Use dated primary project, funder and provider records. Separate what was planned, demonstrated and subsequently delivered.

Primary routes

• RISC-V: CHERIoT study
• CHERI Alliance products