How it works

Technology

Explore capabilities, bounds, permissions and compartmentalisation from first principles to formal evidence.

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01 · Technology Plain-language overview CHERI turns a pointer from a bare address into a protected capability whose validity, bounds and permissions are checked by the processor. Read this page
02 · Technology Sealing Sealing turns a capability into a protected, opaque form associated with a type. Read this page
03 · Technology Formal methods Formal methods use mathematical models and machine-checked reasoning to define and analyse architecture behaviour. Read this page
04 · Technology Bounds Capability bounds describe the memory region an access may address, allowing the processor to stop references that escape an authorised object or range. Read this page
05 · Technology Capabilities A CHERI capability is a protected value that identifies a memory location and carries limits on how it may be used. Read this page
06 · Technology Specifications CHERI specifications define capability behaviour for named architectures and revisions; compatibility claims should always identify the document actually implemented. Read this page
07 · Technology Architectures CHERI is an architectural approach implemented in several instruction-set contexts, including research and development work for MIPS, RISC-V, Arm Morello and the embedded CHERIoT profile. Read this page
08 · Technology Hybrid systems A hybrid CHERI system supports conventional pointers alongside capabilities, allowing selected code or interfaces to adopt capability features while retaining compatibility. Read this page
09 · Technology Permissions Permissions specify which operations a capability authorises, such as loading data, storing data or executing code. Read this page
10 · Technology Temporal memory safety Temporal memory safety prevents code from continuing to use an object after its lifetime has ended. Read this page
11 · Technology Compartmentalisation Compartmentalisation divides software into components that hold only the capabilities needed for their job. Read this page
12 · Technology Spatial memory safety Spatial memory safety means an access stays within the intended object or region. Read this page
13 · Technology Performance CHERI performance is a property of a complete implementation and workload: microarchitecture, capability width and compression, caches, memory, ABI, compiler, operating system and compartment design all contribute. Read this page
14 · Technology Pure-capability systems In a pure-capability ABI, pointers are represented and passed as capabilities throughout the supported software environment. Read this page
15 · Technology Tags and validity A capability's validity is protected by a tag that ordinary memory writes cannot forge. Read this page
16 · Technology Provenance Pointer provenance describes the legitimate origin and derivation of authority to access memory. Read this page