Platforms
Processor and SoC IP
Processor and SoC IP selection determines how capability tags, memory, interconnects, DMA, debug, boot and peripherals preserve the intended CHERI security model.
Overview
Processor and SoC IP selection determines how capability tags, memory, interconnects, DMA, debug, boot and peripherals preserve the intended CHERI security model. A CHERI core is necessary but not sufficient for a CHERI-capable system.
Turn the threat model into integration questions early. Identify every path that can create, store, move or bypass capability-protected data, including caches, interconnects, external memory, DMA, debug and boot. Assign each path to a supplier or system owner.
Best fit
Early system-level requirements prevent secure processor behaviour from being weakened by adjacent components.
What to evaluate
1. Processor profile
Specify architecture revision, privilege model, capability format, interrupts, virtual memory and supported software ABI.
2. System paths
Define tag storage and propagation through caches, memory controllers, interconnects, DMA and external memory.
3. Assurance
Request verification evidence, integration tests, debug policy, update support and clear responsibility across IP suppliers.
Check current status
Integration details and proprietary extensions may materially affect portability and assurance. Review the complete implementation, not a feature checklist.
Verify availability, maturity, specifications, software support and lifecycle terms with the current platform owner before procurement.